//**************************************************
// Description: check the extracted field whether match the register value
//**************************************************

//**************************************************
// include files
//**************************************************
`include "protocol_define.v"
module UDP_field_check (
    input                           clk ,
    input                           rst_n ,
    // UDP deal module
    input                           field_enable ,
    input   [47:0]                  DATALINK_dst_mac_extracted ,
    input   [47:0]                  DATALINK_src_mac_extracted ,
    input   [31:0]                  NETWORK_src_IP_extracted ,
    input   [31:0]                  NETWORK_dst_IP_extracted ,
    input   [15:0]                  TRANSPORT_src_port_extracted ,
    input   [15:0]                  TRANSPORT_dst_port_extracted ,
    output                          field_check_result ,
    output                          field_check_success ,
    // register config
    input   [47:0]                  NP_MAC_address ,
    input   [31:0]                  NP_IP_address ,
    input   [15:0]                  NP_port_address ,
    // FIFO interface
    output                          fifo_wr_en ,
    output  [47:0]                  DATALINK_dst_mac_fifo ,
    output  [47:0]                  DATALINK_src_mac_fifo ,
    output  [31:0]                  NETWORK_src_IP_fifo ,
    output  [31:0]                  NETWORK_dst_IP_fifo ,
    output  [15:0]                  TRANSPORT_src_port_fifo ,
    output  [15:0]                  TRANSPORT_dst_port_fifo
) ;

    //----------------------------------------------
    // output signal register declare
    //----------------------------------------------
    reg                             field_check_result_r ;
    reg                             field_check_success_r ;
    reg                             fifo_wr_en_r ;
    reg     [47:0]                  DATALINK_dst_mac_fifo_r ;
    reg     [47:0]                  DATALINK_src_mac_fifo_r ;
    reg     [31:0]                  NETWORK_src_IP_fifo_r ;
    reg     [31:0]                  NETWORK_dst_IP_fifo_r ;
    reg     [15:0]                  TRANSPORT_src_port_fifo_r ;
    reg     [15:0]                  TRANSPORT_dst_port_fifo_r ;

    //----------------------------------------------
    // output signal behaviour
    //----------------------------------------------
    // check result
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            field_check_result_r <= 1'b0 ;
        else if( field_enable==1'b1 )
            field_check_result_r <= 1'b1 ;
        else 
            field_check_result_r <= 1'b0 ;
    end
    // check success
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            field_check_success_r <= 1'b0 ;
        else if( field_enable==1'b1 ) begin
            if( ( DATALINK_dst_mac_extracted    == NP_MAC_address ) &&  
                ( NETWORK_dst_IP_extracted      == NP_IP_address )  && 
                ( TRANSPORT_dst_port_extracted  == NP_port_address )    )
                field_check_success_r <= 1'b1 ;
            else
                field_check_success_r <= 1'b0 ;
        end
        else 
            field_check_success_r <= 1'b0 ;
    end
    // FIFO write enable
    always @(posedge clk or negedge rst_n) begin
        if( !rst_n )
            fifo_wr_en_r <= 1'b0 ;
        else if( field_check_success_r==1'b1 )
            fifo_wr_en_r <= 1'b1 ;
        else
            fifo_wr_en_r <= 1'b0 ;
    end
    // FIFO write data
    always @(posedge clk or negedge rst_n) begin
        if( !rst_n ) begin
            DATALINK_dst_mac_fifo_r <= 48'b0 ;
            DATALINK_src_mac_fifo_r <= 48'b0 ;
            NETWORK_src_IP_fifo_r <= 32'b0 ;
            NETWORK_dst_IP_fifo_r <= 32'b0 ;
            TRANSPORT_src_port_fifo_r <= 16'b0 ;
            TRANSPORT_dst_port_fifo_r <= 16'b0 ;
        end
        else if( field_check_success_r==1'b1 ) begin
            DATALINK_dst_mac_fifo_r <= DATALINK_dst_mac_extracted ;
            DATALINK_src_mac_fifo_r <= DATALINK_src_mac_extracted ;
            NETWORK_src_IP_fifo_r <= NETWORK_src_IP_extracted ;
            NETWORK_dst_IP_fifo_r <= NETWORK_dst_IP_extracted ;
            TRANSPORT_src_port_fifo_r <= TRANSPORT_src_port_extracted ;
            TRANSPORT_dst_port_fifo_r <= TRANSPORT_dst_port_extracted ;
        end
        else begin
            DATALINK_dst_mac_fifo_r <= 48'b0 ;
            DATALINK_src_mac_fifo_r <= 48'b0 ;
            NETWORK_src_IP_fifo_r <= 32'b0 ;
            NETWORK_dst_IP_fifo_r <= 32'b0 ;
            TRANSPORT_src_port_fifo_r <= 16'b0 ;
            TRANSPORT_dst_port_fifo_r <= 16'b0 ;
        end
    end



    //----------------------------------------------
    // output signal assign
    //----------------------------------------------
    assign field_check_result = field_check_result_r ;
    assign field_check_success = field_check_success_r ;
    assign fifo_wr_en = fifo_wr_en_r ;
    assign DATALINK_dst_mac_fifo = DATALINK_dst_mac_fifo_r ;
    assign DATALINK_src_mac_fifo = DATALINK_src_mac_fifo_r ;
    assign NETWORK_src_IP_fifo = NETWORK_src_IP_fifo_r ;
    assign NETWORK_dst_IP_fifo = NETWORK_dst_IP_fifo_r ;
    assign TRANSPORT_src_port_fifo = TRANSPORT_src_port_fifo_r ;
    assign TRANSPORT_dst_port_fifo = TRANSPORT_dst_port_fifo_r ;
endmodule